module ysyx_050369_as (
    input         clk,
    input         rst,
    input         as_valid,
    input         as_ready,
    input         ex2as_valid,
    output        as2wb_valid,
    input         i_wb_fence,
    output        o_fdone,
    // input         wb2as_ready,
    input  [31:0] i_pc,
    input  [31:0] i_inst,
    input         i_reg_wen,
    input [4 :0]  i_reg_waddr,
    input [63:0]  i_reg_res,
    input         i_mem_wen,
    input [31:0]  i_mem_waddr,
    input [63:0]  i_mem_wdata,
    input [7 :0]  i_mem_wmask,
    input         i_mem_ren,
    input [31:0]  i_mem_raddr,
    input [7 :0]  i_mem_rmask,
    input [63:0]  i_ctreg_data,


    output   [31:0] o_inst, 
    output   [63:0] o_mem_rdata, 
    output   [31:0] o_mem_raddr, 
    output          o_mem_ren, 
    output          as2wb_dev,

    output   [63:0] o_reg_wdata, 
    output          o_reg_wen, 
    output   [4:0]  o_reg_waddr,
//to reg sb
    output          o_as0_wen,
    output [4:0]    o_as0_waddr,
    output [63:0]   o_as0_wdata,
    output          o_as0_memren,
    output [31:0]   o_as0_memaddr,
    output [7 :0]   o_as0_memmask,
    output [127:0]  o_cache_data,
    output          o_as0_memwen,
`ifdef ysyx_050369_SOC
    output [5:0]    io_sram0_addr,
	output          io_sram0_cen,
	output          io_sram0_wen,
	output [127:0]  io_sram0_wmask,
	output [127:0]  io_sram0_wdata,
	input [127:0]   io_sram0_rdata,
	output [5:0]    io_sram1_addr,
	output          io_sram1_cen,
	output          io_sram1_wen,
	output [127:0]  io_sram1_wmask,
	output [127:0]  io_sram1_wdata,
	input [127:0]   io_sram1_rdata,
    output [5:0]    io_sram2_addr,
	output          io_sram2_cen,
	output          io_sram2_wen,
	output [127:0]  io_sram2_wmask,
	output [127:0]  io_sram2_wdata,
	input [127:0]   io_sram2_rdata,
    output [5:0]    io_sram3_addr,
	output          io_sram3_cen,
	output          io_sram3_wen,
	output [127:0]  io_sram3_wmask,
	output [127:0]  io_sram3_wdata,
	input [127:0]   io_sram3_rdata,
`else 
    output   [31:0] o_pc, 
`endif 
    ///////////////////////////////////
	output  [2:0]   size_t,
    output          axi_read ,
    output          unbrust,
    output          uncache,
    output  [31:0]  dc_raddr,
    output  [31:0]  dc_waddr,
    output  [7 :0]  wstrb_t,
    output 			axi_write,
    output [31:0]   dirty_addr,
    output 	[127:0] dc_wdata,

    input   [127:0] i_axi_data,
    input           i_axi_wen ,
    input           wdone,
    input           rdone,
    output          axi_stop
);
assign as2wb_valid= as_valid;
    reg [31:0]pc,inst;
    reg         reg_wen;
    reg [4 :0]  reg_waddr;
    reg [63:0]  reg_res;
    reg         mem_wen;
    reg [31:0]  mem_waddr;
    reg [63:0]  mem_wdata;
    reg [7 :0]  mem_wmask;
    reg         mem_ren;
    reg [31:0]  mem_raddr;
    reg [7 :0]  mem_rmask;
    reg [63:0]  ctreg_data;
    always @(posedge clk) begin
        if (rst || ~as_valid) begin
            mem_wen     <= 'b0;
            mem_waddr   <= 'b0;
            mem_wdata   <= 'b0;
            mem_wmask   <= 'b0;
            mem_ren     <= 'b0;
            mem_raddr   <= 'b0;
            mem_rmask   <= 'b0;
            pc          <= 'b0;
            inst        <= 'b0;
            reg_wen     <= 'b0;
            reg_waddr   <= 'b0;
            reg_res     <= 'b0;
            ctreg_data  <= 'b0;
        end
        else  begin
            if (ex2as_valid&&as_ready) begin
                reg_wen     <= i_reg_wen;
                reg_waddr   <= i_reg_waddr;
                reg_res     <= i_reg_res;
                mem_wen     <= i_mem_wen;
                mem_waddr   <= i_mem_waddr;
                mem_wdata   <= i_mem_wdata;
                mem_wmask   <= i_mem_wmask;
                mem_ren     <= i_mem_ren;
                mem_raddr   <= i_mem_raddr;
                mem_rmask   <= i_mem_rmask;
                pc          <= i_pc;
                inst        <= i_inst;
                ctreg_data  <= i_ctreg_data;
            end
        end
    end
    assign o_as0_wen    = reg_wen; 
    assign o_as0_waddr  = reg_waddr;
    assign o_as0_wdata  = reg_res;
    assign o_as0_memren = mem_ren;
    assign o_as0_memaddr = mem_raddr;
    assign o_as0_memmask = mem_rmask;
    assign o_as0_memwen   = mem_wen;
    wire ctreg_valid;
    // assign ctreg_valid = (mem_raddr>=32'h2000000)&&(mem_raddr<=32'h200FFFF);
    assign ctreg_valid =( mem_raddr[31:16] == 16'h2000);
    wire stop_dcache;
    assign stop_dcache = ~as_ready;
ysyx_050369_dcache dcache(
    .clk            (clk),
    .rst            (rst),
    .flush          (1'b0),
    .i_stop         (stop_dcache),
    .i_wb_fence     (i_wb_fence),
    .i_mem_wen      (mem_wen),
    .i_mem_waddr    (mem_waddr),
    .i_mem_wdata    (mem_wdata),
    .i_mem_wmask    (mem_wmask),
    .i_mem_ren      (mem_ren),
    .i_mem_raddr    (mem_raddr),
    .i_mem_rmask    (mem_rmask),
    .o_mem_rdata    (o_mem_rdata),
    .o_fdone        (o_fdone),
    .i_pc           (pc),
    .i_inst         (inst),
    .i_reg_wen      (reg_wen),
    .i_reg_waddr    (reg_waddr),
    .i_reg_res      (reg_res),
    .i_ctreg_valid  (ctreg_valid),
    .i_ctreg_data   (ctreg_data),
    .o_inst         (o_inst), 
    .o_reg_wdata    (o_reg_wdata), 
    .o_reg_wen      (o_reg_wen), 
    .o_reg_waddr    (o_reg_waddr),
    .o_mem_ren      (o_mem_ren),
    .o_mem_raddr    (o_mem_raddr),
    .o_dev          (as2wb_dev),
    .o_cache_data   (o_cache_data),
`ifdef ysyx_050369_SOC
    .io_sram0_addr  (io_sram0_addr),
	.io_sram0_cen   (io_sram0_cen),
	.io_sram0_wen   (io_sram0_wen),
	.io_sram0_wmask (io_sram0_wmask),
	.io_sram0_wdata (io_sram0_wdata),
	.io_sram0_rdata (io_sram0_rdata),
	.io_sram1_addr  (io_sram1_addr),
	.io_sram1_cen   (io_sram1_cen),
	.io_sram1_wen   (io_sram1_wen),
	.io_sram1_wmask (io_sram1_wmask),
	.io_sram1_wdata (io_sram1_wdata),
	.io_sram1_rdata (io_sram1_rdata),
    .io_sram2_addr  (io_sram2_addr),
	.io_sram2_cen   (io_sram2_cen),
	.io_sram2_wen   (io_sram2_wen),
	.io_sram2_wmask (io_sram2_wmask),
	.io_sram2_wdata (io_sram2_wdata),
	.io_sram2_rdata (io_sram2_rdata),
    .io_sram3_addr  (io_sram3_addr),
	.io_sram3_cen   (io_sram3_cen),
	.io_sram3_wen   (io_sram3_wen),
	.io_sram3_wmask (io_sram3_wmask),
	.io_sram3_wdata (io_sram3_wdata),
	.io_sram3_rdata (io_sram3_rdata),
`else 
    .o_pc           (o_pc), 
`endif 
	.size_t         (size_t),
    .axi_read       (axi_read),
    .unbrust        (unbrust),
    .uncache        (uncache),
    .i_raddr        (dc_raddr),
    .i_waddr        (dc_waddr),
    .wstrb_t        (wstrb_t),
    .axi_write      (axi_write),
    .dirty_addr     (dirty_addr),
    .i_wdata        (dc_wdata),
    .i_axi_data     (i_axi_data),
    .i_axi_wen      (i_axi_wen),
    .wdone          (wdone),
    .rdone          (rdone),
    .axi_stop       (axi_stop)
);

endmodule